Utilisateur:Topeil/Asynchronous circuit

An asynchronous circuit, or self-timed circuit, is a digital circuit which is not governed by a clock circuit or global clock signal. Instead they often use signals that indicate completion of instructions and operations, specified by simple data transfer protocols.

This digital logic design is contrasted with a synchronous circuit which operates according to clock timing signal. Synchronous circuit are much more common, and most circuits are synchronous today, but asynchronous design may be useful to reduce power consumption since the clock signal consumes a lot of power. It may have other assets, such as increased speed, easier and faster design process, and robustness.

As of 2012, despite it, most integrated circuits produced are synchronous. For example, the vast majority of processors have a clock, even if there are some asynchronous microcontrollers.

Properties

Power consumption

As a clock signal is constantly changing its state, it may account for a big part of the power consumption. Asynchronous circuits are active only when data is available. Else, no transistor switches and most power consumption comes from subthreshold leakage current. This makes asynchronous design suitable to build low power devices or when the circuit alternates between sleeping and calculating mode. But in order to ensure local handshaking between their components, asynchronous circuits use more wires and transistors than their synchronous counterpart, which causes power wastes.

Some asynchronous circuits have shown power consumption improvements: an implementation of the 8051 microcontroller architecture uses a quarter of the power of an equivalent synchronous circuit, while the Amulet processors have power consumption similar to those of synchronous ARM processors using the same technology.

Low electromagnetic emission

Asynchronous circuit emit less electromagnetic noise than synchronous ones. This is used to implement more secure circuits, for example for smartcards, or near an antenna.

Elastic pipelining

Since asynchronous pipelines are synchronized locally, they contain a variable number of data tokens.

Communication protocols

There are several ways to create asynchronous communication channels. Usually, the sender signals the availability of data with a request, Req, and the receiver indicates completion with an acknowledgement signal, Ack, indicating that it is able to process new requests; this process is called a handshake. The differences lie in the way this signals are coded.

Protocols

There are two protocol families in asynchronous circuits, which differ in the way events are encoded:

• They may be represented by any transition on a wire, from 0 to 1 as well as 1 to 0. This is called transition signalling, the two-phase protocol, a half-handshake or Non-Return-to-Zero encoding
• Or the signals may require a reset before other operations are performed. For example, the sender resets the request wires once the acknoledgement is received, and the receiver resets the acknowledgement afterwards. This is the four-phase protocol, or Return-to-Zero encoding. Despite being apparently more complicated, the circuit-level implementations are usually faster and simpler.

This basic distinction doesn't account for the wide variety of protocols. These events may encode requests and acknowledgements only or encode the data, which leads to the popular multi-wire encodings. A lot of other, less common protocols have been proposed. Those include using a single wire for request and acknowledgment, using several significant voltages, using only pulses or balance timings in order to remove the latches.

Data encoding

There are several ways to encode data in asynchronous circuits. The most obvious encoding, similar to what can be found in synchronous circuits, is the bundled-data encoding, which uses one wire per bit of data and a separate request wire. Another common way to encode the data is to use multiple wires to encode a single digit: the value is determined by the wire on which the event occurs. This avoid some of the delay assumptions necessary with bundled-data encoding, since the request and the data are not separated anymore.

Bundled-data encoding

This is the same encoding as in synchronous circuits: it uses one wire per data bit. The request and the acknowledgement are sent on separate wires with various protocols. These circuits usually assume a bounded delay model, the completion signals being delayed long enough for the calculations to take place.

Such circuits are often referred to as micropipelines, whether they use a two-phase or four-phase protocol, even if the word was initially introduced for two-phase bundled-data.

Multi-rail encoding

Here, the request isn't sent on a dedicated wire: it is implicit, when a transition happens on one wire. Any m of n encoding can be used, where a digit is represented by m transitions on n wires, and the reception of these transitions is equivalent to a request, with the advantage that this communication is delay-insensitive. Usually, a one-hot (1 of n) encoding is preferred. They can represent a digit in radix n.

Dual-rail encoding is by far the most common, mainly four-phase, which is also called three-state encoding, since it has two valid states (10 and 01, after a transition) and a reset state (00). Another common encoding, which leads to simpler implementation than one-hot two-phase dual-rail, is four state encoding, or level encoded dual-rail, which uses a data bit and a parity bit to achieve two-phase encoding.